Vhdl фазовращатель на двух сдвиговых регистрах

	
	-- счетчики задержки
	signal s_clk_shift_rs	: std_logic_vector(7 downto 0);	
	signal s_clk_shift_fl	: std_logic_vector(7 downto 0);	
	-- счетчики элементов цепи фазовр.
	signal s_nb_shift_rs	: std_logic_vector(3 downto 0);	
	signal s_nb_shift_fl	: std_logic_vector(3 downto 0);	
	-- исходный цифровой сигнал  
	signal s_gn_chirp_tm	: std_logic;
	--выходы цепи фазовращателей
	signal s_gn_chirp_rs	: std_logic_vector(13 downto 0);	
	signal s_gn_chirp_fl	: std_logic_vector(13 downto 0);	
      --
	signal s_chirp_rs	: std_logic;	
	signal s_chirp_fl	: std_logic;	
	-- 				
	signal s_bl_rs		: std_logic;
	signal s_bl_fl		: std_logic;

      -- процесс на фазовращателях
	process(clk, clr)
	begin
		if clk'event and clk = '1' then
		if clr = '0' or enable = '0' then 
			s_gn_chirp_rs <= (others => '0');
			s_clk_shift_rs <= (others => '0');
			s_clk_shift_fl <= (others => '0');
			s_nb_shift_rs <= (others => '0'); 
			s_nb_shift_fl <= (others => '0'); 
			s_bl_rs <= '0'; 
			s_bl_fl <= '1'; 
			s_chirp_rs <= '0';
			s_chirp_fl <= '1';
			s_gn_chirp_fl <= "11111111111111";
		else 
			if s_bl_rs = '0' and s_gn_chirp_tm = '1' then
				s_chirp_rs <= '1';
				s_bl_rs <= '1';
				s_bl_fl <= '0';
				s_gn_chirp_rs <= "00000000000001";
				s_gn_chirp_fl <= "11111111111111";
				s_clk_shift_rs <= (others => '0'); 
				s_nb_shift_rs <= "0001";
			end if;	
     		if s_bl_rs = '1' then
				s_clk_shift_rs <= s_clk_shift_rs + 1;
				if s_clk_shift_rs = 24 then
					s_clk_shift_rs <= (others => '0');	
					s_nb_shift_rs <= s_nb_shift_rs + 1;	
					s_gn_chirp_rs(13 downto 1) <= s_gn_chirp_rs(12 downto 1) & s_chirp_rs;
					if s_nb_shift_rs = 13 then
						s_nb_shift_rs <= (others => '0');
						s_bl_rs <= '0'; 	
					end if;
				end if;
			end if;	
			if s_bl_fl = '0' and s_gn_chirp_tm = '0' then
				s_chirp_fl <= '0';
				s_bl_fl <= '1'; 
				s_gn_chirp_fl <= "11111111111110";
				s_clk_shift_fl <= (others => '0'); 
				s_nb_shift_fl <= "0001";
			end if;	
			if s_bl_fl = '1' then
				s_clk_shift_fl <= s_clk_shift_fl + 1;
				if s_clk_shift_fl = 24 then 
					s_clk_shift_fl <= (others => '0');	
					s_nb_shift_fl <= s_nb_shift_fl + 1;	
					s_gn_chirp_fl(13 downto 1) <= s_gn_chirp_fl(12 downto 1) & s_chirp_fl;
					if s_nb_shift_fl = 13 then
						s_nb_shift_fl <= (others => '0');	
						s_bl_fl <= '1'; 
						s_gn_chirp_rs <= "00000000000000";
					end if;
				end if;
			end if;
		end if;
		end if;
	end process;
	
	-- выходы фазовращателя
	gn_chirp <= s_gn_chirp_rs and s_gn_chirp_fl;